<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>2609.04895v1 on Jaehun's Blog</title><link>https://jaehun.me/en/tags/2609.04895v1/</link><description>Recent content in 2609.04895v1 on Jaehun's Blog</description><generator>Hugo</generator><language>en-US</language><lastBuildDate>Wed, 09 Sep 2026 03:22:44 +0000</lastBuildDate><atom:link href="https://jaehun.me/en/tags/2609.04895v1/index.xml" rel="self" type="application/rss+xml"/><item><title>Cache-Aware Joint Router Adaptation for Memory-Efficient MoE Inference</title><link>https://jaehun.me/en/posts/cache-aware-joint-router-adaptation-for-memory-efficient-moe-inference/</link><pubDate>Wed, 09 Sep 2026 00:00:00 +0900</pubDate><guid>https://jaehun.me/en/posts/cache-aware-joint-router-adaptation-for-memory-efficient-moe-inference/</guid><description>&lt;p&gt;&lt;a&#10; href="https://arxiv.org/abs/2609.04895v1"target="_blank"&#10; class="inline-flex items-center gap-1"&#10; &gt;Paper&lt;svg class="h-3 w-3 flex-shrink-0" id="external-link" xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24"&gt;&lt;path fill="none" stroke="currentColor" stroke-linecap="round" stroke-linejoin="round" stroke-width="2" d="M15 3h6v6m-11 5L21 3m-3 10v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6"/&gt;&lt;/svg&gt;&#10; &lt;/a&gt;&lt;/p&gt;&#10;&lt;h2 id="cache-learning-routers-cache-aware-joint-router-adaptation-for-memory-constrained-moe-inference"&gt;Cache-Learning Routers: Cache-Aware Joint Router Adaptation for Memory-Constrained MoE Inference&lt;a href="#cache-learning-routers-cache-aware-joint-router-adaptation-for-memory-constrained-moe-inference" class="heading-anchor" aria-label="Link to this section"&gt;&lt;svg class="h-4 w-4" aria-hidden="true" xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24"&gt;&lt;g fill="none" stroke="currentColor" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"&gt;&lt;path d="M10 13a5 5 0 0 0 7.54.54l3-3a5 5 0 0 0-7.07-7.07l-1.72 1.71"/&gt;&lt;path d="M14 11a5 5 0 0 0-7.54-.54l-3 3a5 5 0 0 0 7.07 7.07l1.71-1.71"/&gt;&lt;/g&gt;&lt;/svg&gt;&lt;/a&gt;&lt;/h2&gt;&lt;h2 id="tldr"&gt;TL;DR&lt;a href="#tldr" class="heading-anchor" aria-label="Link to this section"&gt;&lt;svg class="h-4 w-4" aria-hidden="true" xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24"&gt;&lt;g fill="none" stroke="currentColor" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"&gt;&lt;path d="M10 13a5 5 0 0 0 7.54.54l3-3a5 5 0 0 0-7.07-7.07l-1.72 1.71"/&gt;&lt;path d="M14 11a5 5 0 0 0-7.54-.54l-3 3a5 5 0 0 0 7.07 7.07l1.71-1.71"/&gt;&lt;/g&gt;&lt;/svg&gt;&lt;/a&gt;&lt;/h2&gt;&lt;p&gt;Starting from the observation that MoE&amp;rsquo;s real bottleneck is not compute but expert-weight movement, this work proposes the &lt;strong&gt;Temporal Router&lt;/strong&gt; and &lt;strong&gt;Spatio-Temporal Router&lt;/strong&gt;, which learn the cache-residency priority itself via post-training while keeping the native Top-$K$ selection rule unchanged (source: §1). On Qwen3-30B-A3B-Instruct-2507, the Temporal-only mode achieves hit-rate gains of +10.46~+33.34 pp and traffic reductions of -28.0~-79.9% over classic replacement policies, with zero additional proactive loads ($P=0$ MB/token); the full mode records adjusted hit-rate gains of +1.15~+18.03 pp and per-token load reductions of -4.6~-53.3% over the strongest prefetch baseline, ProMoE (source: Tab.1, §4.2).&lt;/p&gt;</description></item></channel></rss>