[Paper Review] Helix Parallelism: Rethinking Sharding Strategies for Interactive Multi-Million-Token LLM Decoding

Paper Link

Helix Parallelism: Breaking the Latency-Throughput Wall of Ultra-Long LLM Decoding

TL;DR

Helix Parallelism schedules Attention and FFN with different parallelism strategies to eliminate KV cache duplication and FFN weight load bottlenecks—reducing token latency by up to 1.5× for 1M-token contexts and increasing concurrent user capacity by up to 32× under the same latency budget.

Core Idea

2-D Sharding + Communication Hiding During the Attention phase, Helix applies KV Parallelism (sequence-wise) × Tensor Parallelism (head-wise) to achieve 0% KV duplication. Then, the same GPU pool is reshaped into Tensor(×Expert) Parallelism for the FFN phase to distribute weight loading evenly. All-to-All communication between these two phases is overlapped using a HOP-B pipeline, minimizing exposed latency.

Background: The Problem They Solved

When serving large LLMs in “real-time”, two bottlenecks arise simultaneously:

BottleneckCausePrior SolutionsLimitation
KV Cache DuplicationIf TP degree > number of KV heads K, each GPU must replicate the entire KV cacheTP, PPDRAM traffic and memory usage surge → Latency plateau
FFN Weight LoadingWith KV cache sharded (e.g., via KVP), FFN computation gets stuck on a few GPUsKVP (e.g., Medha)Solves KV, but FFN dominates the tail of TTL

Ultimately, existing methods were stuck in a trade-off:
“Shard KV → FFN bottlenecks, shard FFN → KV duplicates.”

New Approach: Helix Parallelism

Helix divides time within a single layer:

  1. Attention PhaseKV Parallelism (sequence) × Tensor Parallelism (head)

    • FlashAttention is performed per KV slice

    • Each slice outputs Oᵢ and log-sum-exp LSEᵢ

    • Final softmax is restored using:

      $$ O = \frac{\sum_i O_i,e^{\text{LSE}_i}}{\sum_i e^{\text{LSE}_i}} $$

  2. FFN Phase — The same GPU pool is reshaped into TP (×EP) layout

    • All-to-All followed by 32-way GEMM, then All-Reduce
  3. HOP-B — All-to-All for token t is overlapped with FlashAttention of token t+1

    • Exposed communication ≤ 12% of TTL

How It Works: A Concrete Example

Llama-3 70B | 32 × H100 GPUs (within a single NVLink node)
Q-heads = 64, KV-heads K = 8 → 8 TP × 4 KVP = 32 GPUs

PLAINTEXT

KVP Rows   TP Cols → 0 … 7       (Total 32 GPUs)
Row 0      G0  G1 … G7     (tokens 0 to S/4−1)
Row 1      G8  G9 … G15    (tokens S/4 to S/2−1)
Row 2      G16 G17 … G23   (tokens S/2 to 3S/4−1)
Row 3      G24 G25 … G31   (tokens 3S/4 to S−1)
Click to expand and view more

KV duplication = 0%, KV cache/GPU ≈ 0.3 GB

One Token Flow:

  1. GPU Gr,c runs FlashAttention over its own KV slice → produces (Oᵢ, LSEᵢ)
  2. All-to-All #1: exchange partial outputs across query-head axis
  3. Final softmax is reconstructed from the formula above
  4. Layout switch — All-to-All #2 reshuffles to TP-aligned layout
  5. 32-way TP FFN → All-Reduce #3 aggregates the results
  6. HOP-B — step #1 for token t+1 overlaps with All-to-All of token t

Measured (1M context)
TTL 9.7 ms (vs 11 ms), tok/s/GPU 360 (vs 90),
Concurrent batch capacity increases .

Performance Evaluation: Key Results

ModelHW SetupTTL ↓Batch/Throughput ↑
DeepSeek-R1 671B MoE72 GPUs1.5× ↓32× ↑
Llama-405B Dense72 GPUs1.13× ↓4× ↑
Llama-3 70B (Inference)32 GPUs1.13× ↓4× ↑

Helix points consistently outperform the Pareto frontier defined by TP/KVP/PP baselines.

Our Perspective: Strengths, Limitations, and Why It Matters

Strengths

Limitations

Why It Matters

Real-world LLM services demand low latency + high concurrency.
Helix breaks the existing “KV duplication vs FFN bottleneck” trade-off, enabling large-scale LLMs to be served interactively, with much better throughput and latency balance.

What’s Next?: Future Directions

  1. Integrate Sparse Attention (e.g., NSA) — May cut KV bandwidth by an additional 50%.
  2. Multi-node Helix — Extend to cluster scale with topology-aware All-to-All.
  3. Adaptive Scheduler — Dynamically switch between Helix and traditional TP based on real-time KV/FFN workload balance.
  4. Precision & Quality Evaluation — Validate softmax rescaling stability under FP4/FP8; test for drift and robustness.
  5. Energy & Cost Metrics — Report J·token⁻¹ and $/million tokens to show realistic ROI.

Helix completes a critical piece of the “real-time LLM serving” puzzle.
The remaining pieces—distributed topology, sparse computation, and energy efficiency—will turn million-context LLMs into everyday deployable technology.

Click to toggle detailed LLM Q&A based on this paper.

▶️Click to expand

Prompt 1.1.1 — Research Gap

Analyze the ‘Introduction’ and ‘Related Work’ sections to identify the explicit research gap this study aims to fill, the key limitations of existing approaches, and the state of the art at the time of publication.

Key Conclusion (One-liner)

Existing parallelism methods for ultra-long (≥ 10⁶ tokens) LLM decoding fail to address KV cache duplication and FFN weight-loading bottlenecks simultaneously. Helix Parallelism overcomes both by temporally separating and restructuring the Attention and FFN phases—achieving up to 1.5× lower TTL and 32× higher batch capacity.

1. Unresolved Problems in Prior Work

Prior ApproachCore LimitationResulting Bottleneck
Tensor Parallelism (TP)When TP width > K, each GPU must replicate full KV cacheDRAM bandwidth/memory bloat → Latency plateau
KV Parallelism (Medha)KV is sequence-sharded, but FFN runs on a fixed, small TP group (e.g., 8 GPUs)FFN weight load dominates TTL tail
Sequence/Context Parallelism in training (e.g., USP, LoongServe)Ignores causality + real-time TTL in decodingNot effective for inference with long contexts

→ Thus:

“In real-time, ultra-long context decoding, where both KV and FFN become dominant bottlenecks, there is no method to dynamically reshape parallelism per phase.”

Helix Parallelism directly addresses this dual bottleneck problem.

2. State of the Art at Time of Publication

  • Model/Hardware Context

    • Modern LLMs use GQA/MQA/MLA ⇒ KV heads K ≪ Q-heads Q (e.g., Q = 128, K = 8)
    • NVIDIA GB200 NVL72-class GPUs with FP4 and high NVLink bandwidth
  • Dominant Parallelism Combinations

    1. TP (≤ K): no KV duplication, but limited parallelism → FFN bottleneck
    2. TP (> K): higher parallelism but KV cache is duplicated K times
    3. TP + PP + EP: efficient for prefill, limited TTL gains during decoding
    4. Medha-style KVP: sequence-sharded KV reduces DRAM reads,
      → But FFN still centralized on K GPUs → load imbalance
  • Example Limits

    • When TP > K, KV cache duplication plateaus performance.
    • In Medha+Blackwell, KV duplication is solved, but FFN loading still dominates >50% of TTL (e.g., DeepSeek-R1 MoE).

Helix’s Claimed Improvements (Numerical Summary)

ModelTTL ReductionBatch Capacity ↑Tokens/sec/GPU ↑
DeepSeek-R1 (671B MoE)1.5× ↓32× ↑N/A (same TTL, higher B)
Llama-405B (Dense)1.13× ↓4× ↑4× ↑

In short, Helix pushes past the SOTA frontier by sharding KV via KVP while reconfiguring the same GPU pool for FFN using TP(×EP), forming a temporal 2-phase pipeline.

Summary: Existing TP/KVP models solve either KV duplication or FFN load—but not both.
Helix Parallelism introduces per-phase sharding strategies to overcome both simultaneously, achieving real-time LLM inference even with million-token contexts.

Prompt 1.1.2 — Core Hypothesis

What is the central hypothesis of this paper?

The authors hypothesize that by applying Helix Parallelism (including communication-hiding via HOP-B), they can simultaneously eliminate KV cache duplication and FFN weight-loading bottlenecks in ultra-long (≥10⁶ tokens) LLM decoding, reducing token-to-token latency by up to 1.5× and increasing batch capacity by up to 32× under the same latency budget.

Prompt 1.2.1 — Key Contributions

List the top 1–3 most distinctive contributions made by this paper. For each, specify whether it introduces a new architecture, training method, theoretical insight, dataset, or novel application of existing methods.

Summary in One Line

Helix Parallelism and HOP-B reduce TTL by up to 1.5× and boost concurrent decoding by up to 32× in multi-million-token LLM inference.

#ContributionTypeKey Impact / Metric
1Helix Parallelism — Attention uses KV Parallelism (sequence) × Tensor Parallelism (head) to remove KV duplication; FFN reshapes same GPU pool for TP(×EP)💡 New architectural component (hybrid spatial-temporal sharding pipeline)• KV duplication = 0%, FFN load distributed
• TTL ↓ 50%, B ↑ 32×
2HOP-B (Helix Overlap Pipeline - Batchwise) — overlaps All-to-All communication with next token’s computation💡 New architectural component (communication overlap)• Communication latency ≤ 12% of TTL
32D Roofline Analysis + 100k Simulation for Pareto Frontier Discovery — quantifies dual bottleneck & justifies Helix design🧠 Theoretical insight + ⚙️ novel application of simulation-based performance modeling• Visualizes DRAM-limited KV/FFN regime, positions Helix as Pareto-optimal

In short: Helix Parallelism enables per-phase tailored sharding; HOP-B hides communication latency; and the authors ground this with simulation-backed bottleneck modeling and empirical evidence.

Prompt 1.2.2 — Author’s Perspective on Strengths

Why do the authors believe their method is superior to prior work?

Summary | The authors claim that Helix Parallelism breaks through the “dual bottlenecks” of KV cache duplication and FFN weight loading by applying phase-wise customized sharding and communication hiding (HOP-B), achieving up to 1.5× lower latency and 32× more concurrent users.

#Why It’s Better (Author’s Argument)Supporting Evidence
1“Solves both KV and FFN bottlenecks”
– KV is sharded by sequence (KVP), FFN distributed via TP/EP reshaping
Roofline plots show Helix avoids KV duplication plateau
2“HOP-B hides communication latency”
– All-to-All overlapped with next token’s computation
Ablation: TTL drops by 12% on Llama-405B with HOP-B enabled
3“Helix pushes beyond existing Pareto frontier”
– Provides better latency and throughput simultaneously across models and workloads
Simulations show Helix dominates prior TP/KVP configurations

Additional Evidence (from text)

  • Memory-independent All-to-All traffic: proportional to B·H, not sequence length S → scales to 1M+ tokens
  • Compatible with modern GPU features: FP4, GQA, MLA, MoE, NVLink bandwidth
  • Medha vs Helix: Medha still bottlenecks on FFN even after solving KV

The key strength emphasized is that Helix temporally separates Attention (memory-bound) and FFN (compute-bound) phases, and applies phase-specific parallelism to optimize both.

Prompt 1.3.1 — Step-by-Step Algorithm Explanation

Explain the core algorithm or method step by step, using a toy example with clearly defined variables.

Summary | Helix applies KVP × TP sharding for memory-efficient Attention and reshapes the same GPU pool for TP (×EP) in FFN, with HOP-B overlapping communication to hide latency—resulting in TTL ↓ up to 1.5× and batch ↑ up to 32×.

1. Quick Glossary

SymbolMeaning
BBatch size
SSequence length
Q/KQuery / KV head count
HHidden size
G# of GPUs = TP × KVP
TPTensor Parallelism (head dimension)
KVPKV Parallelism (sequence dimension)
EPExpert Parallelism (for MoE)
TTLToken-to-token latency

2. Helix Workflow by Step

StepGPU LayoutDescription
① Attention (TP ≤ K, KVP > 1)TP splits heads, KVP splits sequence → G = TP × KVP1. All GPUs compute QKV projection → each holds its KV slice (S/KVP)
2. FlashAttention per slice → produces Oᵢ and LSEᵢ
3. All-to-All #1 across query heads
4. Rescaling with softmax formula for exact output
② HOP-Bsame layoutOverlaps All-to-All of token t with FlashAttention of token t+1 → hides communication time
③ FFN (Dense: TPF = G)reshaped to TP × EP layout1. All-to-All #2 to redistribute activations
2. Local FFN GEMMs (routing for MoE)
3. All-Reduce #3 to aggregate output
4. Forward to next layer, layout switches back to Attention

→ KV read ∝ S/KVP, FFN load ∝ 1/G → both bottlenecks are mitigated.

3. Toy Example Walkthrough (B = 1, S = 4, Q = 4, K = 2, H = 6, G = 2)

2 GPUs, TP = 2, KVP = 1

  • Input query vector: q = [1, 0, 1, 0, 0, 1]
  • KV cache (4×6): GPU0 holds tokens 0–1, GPU1 holds tokens 2–3
GPUKV slice① dot(q, K) = α② softmax(α)③ α · V → o_partial
0tokens 0–1[3, 2][0.73, 0.27]0.73·v₀ + 0.27·v₁
1tokens 2–3[1, 4][0.12, 0.88]0.12·v₂ + 0.88·v₃
  • All-to-All exchanges o_partial and LSE
  • Final o_final is reconstructed using the formula

HOP-B overlaps token t communication with token t+1 computation.

FFN Phase:

  • All-to-All reshapes hidden vector (dim 6): GPU0 gets dims 0–2, GPU1 gets dims 3–5
  • Each runs FFN (W₁·h + b → GeLU → W₂·…) → then All-Reduce
  • Final hidden vector h′ is produced

This process is repeated every token, keeping KV duplication at 0% and FFN load balanced.

4. Key Results Summary

ModelGTTL ↓Batch ↑Notes
DeepSeek-R1 (671B MoE)721.5× ↓32× ↑
Llama-405B (Dense)721.13× ↓4× TPS/GPU ↑

Key Takeaways

  1. 2-D Sharding: TP (head) × KVP (sequence) removes KV duplication plateau.
  2. GPU Reuse: Attention → FFN reshaping allows for full GPU utilization.
  3. HOP-B: Hides communication in parallel with compute; reduces visible latency to ≤12%.
  4. Result: Extends the latency-throughput Pareto frontier for ultra-long context LLMs.

Prompt 1.3.2 — The “Secret Weapon”

Identify the single most critical formula, algorithm step, or architectural element enabling the paper’s main contribution.

Summary First

The “secret weapon” of Helix is the LSE-based rescaling of partial Attention outputs from each KV slice:

$$ \boxed{;O=\frac{\sum_{i=1}^{N} O_i,e^{\text{LSE}i}}{\sum{i=1}^{N} e^{\text{LSE}_i}};} $$

This exact rescaling, performed after a single All-to-All communication round, enables Helix’s KVP × TP 2-D sharding while preserving numerical correctness.

1. What does it do?

StepDescriptionResult
① Per-KVP GPURuns FlashAttention on its KV slice (S/KVP) → emits Oᵢ, LSEᵢMemory-local compute, no KV duplication
② All-to-AllExchange Oᵢ and LSEᵢ across query-head dimensionTraffic ∝ B·H, independent of sequence length S
③ RescalingUse the above formula to reconstruct final softmax output exactlyBitwise equivalent to single-GPU computation
④ Layout SwitchAfter rescaling, output is already in TP layout → ready for FFN phaseEnables immediate FFN parallelism

2. Why is it essential?

  1. Eliminates KV Duplication

    • Even if TP > K, no KV replication needed → avoids DRAM/memory bottleneck
  2. Constant-Time Communication

    • All-to-All cost is independent of context length S; latency hidden via HOP-B
  3. Enables GPU Reuse

    • Output already TP-aligned → immediate transition to FFN phase without reshuffling
  4. Numerical Stability

    • Fully reconstructs softmax normalization without approximation, even at FP4/FP8

In short: this LSE-based partial output recombination is what makes Helix’s dual sharding + GPU reuse architecture possible—without it, the approach collapses.

Prompt 1.4.1 — Key Results with Metrics

Analyze key results from the paper. What metrics were used? What benchmarks? What results do the authors highlight most?

TL;DR

Helix Parallelism pushes the latency-throughput Pareto frontier outward:
It reduces TTL by 1.5× for DeepSeek-R1 and 1.13× for Llama-405B,
while enabling 32× and more concurrent users respectively under the same latency constraint.

1. Key Evaluation Metrics

MetricDefinitionPurpose
TTLToken-to-token latencyReal-time responsiveness
Throughput per GPUTokens generated per second per GPUResource efficiency
Batch ScalabilityNumber of concurrent sequences that can be processed at target TTLScalability for large services

2. Benchmarks & Environment

  • Models
    • DeepSeek-R1 (671B MoE, MLA)
    • Llama-405B (Dense, GQA with Q = 128, K = 8)
  • Context Length: 1M tokens
  • Hardware: Simulated NVIDIA GB200 NVL72
  • Simulation: 100k+ parallelism configurations exhaustively explored (TP, PP, EP, KVP)

3. Summary Table of Core Results

ModelMetricBaseline BestHelixGain
DeepSeek-R1TTL (↓)1.0×0.67×1.5× ↓
Batch Capacity (↑)32×32× ↑
Llama-405BTTL (↓)1.0×0.88×1.13× ↓
TPS/GPU (↑)4× ↑

Interpretation: Helix avoids both KV duplication and FFN bottlenecks, thus dominating the prior Pareto frontier.

4. HOP-B Ablation (Communication Hiding Effect)

ModelHOP-B OFFHOP-B ONTTL Reduction
DeepSeek-R1TTL ↓ 1%Small effect
Llama-405BTTL ↓ 12%Significant gain

HOP-B overlaps token communication with computation, recovering up to 12% TTL.

5. Key Takeaways from Results

  • Helix outperforms all prior sharding combinations on simulated 1M-token settings
  • Throughput ↑, TTL ↓ — a rare simultaneous win
  • Communication cost stays low even with growing context due to B·H-scaling All-to-All

Prompt 1.4.2 — Critical Comparison

How does Helix perform compared to baseline and SOTA methods? Are there cases where it doesn’t outperform others?

Conclusion in One Line

Helix outperforms existing SOTA methods like Medha KVP and TP/PP/EP combinations on both latency and throughput, especially in large-scale, long-context decoding. However, its advantage shrinks in low-GPU or short-context settings.

Model (1M ctx)Baseline ComparedTTL ↓Batch/TPS ↑Author’s Claimed Edge
DeepSeek-R1 (671B, 72 GPUs)Medha KVP + TP(K=8)1.5× ↓32× ↑Solves both KV duplication and FFN load imbalance
Best TP only (K=8)>1.8× ↓32× ↑Allows TP > K without KV duplication
Llama-405B (Dense, G=72)Medha + TP(=8)1.13× ↓4× ↑Avoids KV duplication even with TP > K
Pipeline Parallel (8-stage)>1.3× ↓2–3× ↑PP increases TTL during decoding

📌 Strongest claim: DeepSeek-R1 runs 32× more users concurrently with 1.5× faster latency than the best baseline (Figure 5).

When Helix Doesn’t Win

ObservationHelix ≤ BaselineAuthor’s Explanation
Prefill phaseTP + PP slightly fasterKV cache is short, FFN load dominates → Helix less effective
Small GPU pool (G ≤ K)TP alone is optimalNo KV duplication occurs anyway
Communication-light models (e.g. DeepSeek)HOP-B ON vs OFF: ≤ 1% TTL gainFFN dominates, little communication to hide

Authors emphasize: Helix excels only when KV duplication + FFN bottlenecks coexist.
If G ≤ K or context is short, traditional TP/KVP may suffice.

Summary

  1. Helix dominates in large-scale, long-context decoding (S ≥ 1M, G ≫ K)
  2. In small-scale or short-context scenarios, gains diminish
  3. Therefore, Helix is not a one-size-fits-all, but a specialized tool for large-service inference

Bottom line: Helix shines when both memory (KV) and compute (FFN) become bottlenecks. In simpler regimes, classic TP/PP still hold their ground.

Prompt 1.5.1 — Limitations (Acknowledged & Potential)

What limitations do the authors acknowledge, and what are some others they didn’t mention?

Summary in One Line

Helix removes the KV–FFN bottlenecks cleanly—but it’s heavily dependent on single-node GB200-class GPUs with million-token contexts, and lacks coverage in multi-node, sparse attention, or quality/energy evaluation.

1. Limitations Acknowledged by Authors

TypeDescription
Simulation onlyAll results use a simulator modeled on NVIDIA GB200 NVL72 → may not match real-world HW exactly
Models lack native 1M ctxDeepSeek-R1 and Llama-405B don’t yet support million-token natively, only assumed during testing
Short context, small GPU poolFor S < 4k or G ≤ K, Helix often converges to traditional TP-like behavior
Low communication settingse.g., DeepSeek-R1 → HOP-B makes ≤1% difference
Sparse Attention not supportedNSA and similar methods are left as future work

2. Additional Potential Limitations (Unacknowledged)

ConcernDescription
Single-node assumptionMulti-node All-to-All may reduce HOP-B effectiveness due to inter-node latency
Hardware specificityGB200’s FP4 & NVLink bandwidth are assumed; performance may degrade on PCIe or older GPUs
Runtime layout switching costToken-level reshaping (KVP ↔ TP×EP) requires dynamic memory & communication topology switching
Numerical stability (FP4)No analysis of LSE overflow/underflow risks, especially in long sequences with FP4 precision
Lack of quality evalNo perplexity or BLEU reported; inference quality under FP4 and recombined softmax remains untested
Energy & carbon impactPower draw for 72 GPUs may be high; no energy-per-token or carbon efficiency reported

Summary Takeaways

  • Helix targets “G ≫ K, S ≥ 1M, NVLink-class single node” as its ideal scenario.
  • Sparse Attention, multi-node, precision robustness, and deployment cost/quality are all open areas.
  • Before deploying Helix, verify whether your workload actually faces both KV and FFN bottlenecks.

Prompt 1.5.2 — Future Research Directions

What future work do the authors suggest? What other logical next steps arise from the limitations?

Summary — At a Glance

The authors primarily propose integrating Natively Sparse Attention (NSA) into Helix and extending it into a unified runtime across all context lengths.
Based on the paper’s limitations, we also identify six additional research directions needed for real-world deployment.

1. Explicit Future Work by Authors

IDProposed DirectionExpected Benefit
A1Support Sparse Attention (e.g., NSA)Further reduce KV bandwidth (up to −50%) while preserving 2D sharding structure
A2Unified Runtime across all context lengths (short to long)Simplifies runtime logic by avoiding context-based switching

These are the only two “Future Work” directions explicitly listed by the authors.

2. Additional Research Directions (Derived from Limitations)

LimitationSuggested Future WorkWhy It Matters
Single-node assumptionB1. Multi-node Helix: redesign All-to-All using topology-aware schemes for NVSwitch, PCIe, RDMAMost deployments span racks/clusters; NVLink-only is unrealistic
Variable KV/FFN ratioB2. Adaptive Layout Scheduler: dynamically switch between Helix and traditional TPAvoid Helix overhead when its benefits are marginal (e.g., small S, low G)
FP4 numerical riskB3. Mixed-precision eval: include FP8/BF16; evaluate PPL, BLEU, driftSoftmax rescaling might underflow or overflow in low-precision
Energy cost unmeasuredB4. J/token-aware Helix: report Wh/token, CO₂eq72-GPU deployment likely consumes massive energy; ROI must include cost
HBM-only KV cache assumptionB5. Hierarchical KV Caching + Helix: enable GPU↔CPU↔NVM tiered caching with prefetch supportScaling to 10⁷ tokens will exceed HBM capacity
No output quality comparisonB6. Robustness & Alignment Testing: verify if Helix decoding matches TP output or introduces driftBitwise differences may impact generation quality; no evaluation is present

3. Final Takeaways

  • The authors’ stated goals (A1, A2) focus on expanding Helix to cover sparse attention and runtime unification.
  • For practical deployment, the next steps must address:
    • Inter-node scalability
    • Energy/precision robustness
    • Adaptive dynamic scheduling
    • Memory hierarchy beyond HBM
    • Output quality preservation

These future efforts would extend Helix’s dual-bottleneck breakthroughs to broader, real-world inference scenarios — redefining the new Pareto frontier across latency, throughput, cost, and quality.

Copyright Notice

Author: Jaehun Ryu

Link: https://jaehun.me/en/posts/paper-review-helix-parallelism-rethinking-sharding-strategies-for-interactive-multi-million-token-llm-decoding/

License: CC BY 4.0

This work is licensed under the Creative Commons Attribution 4.0 International License. You are free to use it for any purpose, including commercial use, as long as you provide proper attribution.

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